2.2. Non-algorithmic methods
digital modeling.
The speed of solving a number of complex problems using a program-algorithmic method on a general-purpose digital computer is insufficient and does not satisfy the needs of computer-aided design (CAD) engineering systems. One of these classes of problems, widely used in engineering practice when studying the dynamics (transient processes) of complex automation systems, are systems of high-order nonlinear differential equations in ordinary derivatives. To speed up the solution of these problems, CAD software and hardware systems can include, in addition to the main (leading) general-purpose digital computer, GVMs that are problem-oriented for solving nonlinear differential equations. They are organized on the basis of digital mathematical modeling using a non-algorithmic method. The latter allows you to increase the productivity of CAD due to the inherent parallelism of the computing process, and the discrete (digital) method of representing mathematical quantities allows you to achieve processing accuracy no worse than in a digital computer. These GVMs use two digital modeling methods:
1. Finite-difference modeling;
2. Discharge modeling.
The first method used in GVMs such as digital differential analyzers (DDAs) and digital integrating machines (DIMs) is the well-known method of approximate (step-by-step) finite difference calculations. Digital operating units of the GVM, built on digital circuitry, process fairly small discrete increments of mathematical quantities transmitted along communication lines between operating units. Input and output mathematical quantities are represented, stored, and incremented in digital n-bit codes in up/down counters or accumulator registers.
Increments of all quantities are usually coded in one low-order unit: D:=1ml. R. This corresponds to quantization by level of all processed quantities with a constant quantization step D=1. Consequently, the rate of increase of all machine quantities is limited: |dS/dx|£1.
Signs of single-bit increments are encoded using the sign coding method on two-wire communication lines between operating units:
https://pandia.ru/text/78/244/images/image002_51.gif" width="476" height="64 src=">,
where DSi=yiDx is the increment of the integral in the i-th step of integration, and the i-th ordinate of the subintegral function y(x) – yi is calculated by accumulating its increments:
https://pandia.ru/text/78/244/images/image004_39.gif" width="208" height="56 src=">
with the introduction of a constant normalizing coefficient kn = 2-n, increments at the outputs of the integrators are formed sequentially and processed in the following integrators also sequentially. An exception is the integration of the sum of several integrand functions
https://pandia.ru/text/78/244/images/image006_34.gif" width="239" height="56 src=">
Then, along several m input lines, the lth increments can arrive synchronously at some jth step. For sequential addition, they are spaced within a step using delay lines, increasing the clock frequency of the input accumulating adder by m times. Therefore, the number of summable integrand functions is usually limited to two: m=2.
The structural organization of the digital integrator-adder is very simple. It is constructed in the form of a serial connection of the following functional units:
· 2OR circuit with delay line tз=0.5t at one of the inputs
· input accumulating adder of increments of integrand functions, which accumulates their n-bit ordinates according to input increments:
https://pandia.ru/text/78/244/images/image008_28.gif" width="411" height="194 src=">
When Dх:=(10) the code yk is transmitted without changes, and when Dх:=(01) the output forms a code inverse to the input code yk.
Output accumulating adder, which in each integration step adds to its old contents the contents of the shift register RS of the input NSM (in a serial transmission code, this step is performed in n clock cycles):
· integral output increment generator: DSi:= overflow unit Si, converting the overflow sign into a bipolar increment code (it is most simply implemented if the negative accumulated numbers Si are represented in a modified code: direct, inverse or complementary). The corresponding block diagram of the digital integrator is shown in Fig. 9.14 (p.260) of the textbook. In digital model circuits, the following symbol for a digital adder-integrator is used:
"Zn." indicates the inversion flag (-) if it is required. An important advantage of this method of finite-difference digital modeling is that the same digital integrator, without changing its circuits, is used to perform the linear and nonlinear operations necessary to solve ordinary differential equations. This is explained by the fact that when programming the CDA and CIM, the original equations in derivatives are converted to equations in differentials. Let's look at the simplest digital model programs:
1. multiplying the variable x by the constant k:
Moving on to the differentials dS=кdx, we will make sure that this operation is performed by one integrator with its corresponding initial setting:
3. Multiplication S=xy, or in differentials dS=xdy+ydx.
4.2. trigonometric functions, for example y=sinx, which is a solution to a second order differential equation (since ), or in differentials
 |
DIV_ADBLOCK93">
Considering that the creation of these problem-oriented computers requires significant additional costs, when constructing technical CAD tools, a simpler method of organizing them is often used by combining mass-produced general-purpose digital computers and electronic analog computers (AVMs) built on operational amplifiers into a computing complex . The digital computer and the digital computer are combined using a standard conversion and interface device (CTD), consisting mainly of an ADC and a DAC. A complex problem to be solved is rationally divided into 2 parts between analog and digital processors when programming the complex. Moreover, the analog part is most often problem-oriented at solving differential equations and is used in the general computing process as a fast subroutine.
2.3 Architecture of hybrid computing systems (HCC).
2.3.1. structure of the analog-digital computing complex (ADCC)
GVK or ATsVK is a computing complex consisting of a digital computer and a general-purpose automatic computer, combined using a UPS, and containing in the digital part additional software for automating the programming of the analog part, managing the exchange of information between the analog and digital parts, monitoring and testing the analog part, automation of input-output procedures.
Let's consider the block diagram of an ADCC with the simplest UPS, built on single-channel switched ADCs and DACs. To create the prerequisites for automating AVM programming under the control of a digital computer, the following additional blocks are introduced as part of the AVM hardware:
1. Manually adjustable variable resistances (potentiometers) at the inputs of operational amplifiers in a set of operating units (NOB), known to you from laboratory work on TAU, are replaced with digitally controlled resistances (DCR), which are used as DAC integrated circuits;
 |
For long-term storage of DCC setting codes, a block of buffer registers (BFR) is used, loaded when programming the AVM with digital codes of transmission coefficients (TC) of the operating units, calculated in the digital computer according to the method described in paragraph 2.1; using scale equations of an analogue model;
3. Automatic connection of operating units in accordance with the analog model circuit drawn up in the digital computer (clause 2.1) is carried out by an automatic switching circuit (ASC) using the binary switching vector of the SAC keys, formed in the digital computer and stored during the solution of the problem in the configuration information register (RN) in UPS.
AVM operating modes: preparation, start-up, stop, return to the initial state, output of results to analog peripheral devices (chart recorders, two-coordinate tablet recording devices - DRP) are set from the computer side through the UPS control unit (UPS BU).
The UPS control unit also carries out mutual synchronization of the operation of the digital computer and automatic computer: it transmits external interrupt signals from the analog model to the digital programs of the digital computer, under the control of digital part programs it synchronizes the polling of points in the analog model, the conversion of voltages at these points into digital codes and the transmission of the latter through the BSK and the channel input-output into the RAM of the digital computer; or similarly, the reverse conversion of digital codes into electrical voltages and the supply of the latter to the required points at the inputs of the operating units of the analog model. This principle of functional organization of interaction between the digital and analog parts is supported in hardware by UPS blocks: ADC and DAC, AM and ADM - analog multiplexer and demultiplexer, ML - input and output analog memory blocks built on a variety of similar storage sampling circuits (SSC). The inputs of the input SVX (on the left) are connected to the required points of the analog model circuit (outputs of the corresponding operating blocks). At the necessary discrete moments of time, under the control of a digital computer, individual sample ordinates of analog signals (electrical voltages) are taken from the analog model and stored in the temporary storage system. Then the outputs of the SVR are polled by the AM multiplexer and their output voltages are converted by the ADC into digital codes, which in the direct access mode as a block of numbers (linear array) are written to the OP of the digital computer.
During inverse conversion, the SVX outputs of the second group of the ML output analog memory (on the right) are connected, under the control of the digital computer, to the required inputs of the operating units of the analog model, and the SVX inputs are connected to the outputs of the analog demultiplexer, the input of which is supplied with the output voltage of the DAC. In the direct access mode, a block of numbers is read from the OP of the digital computer. Each of the numbers is converted into an electrical voltage in the DAC, which, under the control of the digital computer with the help of a running ADM, is recorded for storage in one of the temporary storage warehouses. The resulting set of several voltages is stored in several temporary storage systems for a time interval specified by the digital computer program (for example, while solving a problem in the analog part) and is processed by analog operating units.
2.3.2. Methods of organizing analogue -
digital computing.
The principle of alternating operating modes of digital computers and automated computers, reducing the complexity of the control system.
ATsVK are used for analogue-digital modeling of complex automation systems containing control digital computers, as well as for accelerating the solution of complex mathematical problems that require excessive consumption of memory resources and computer computer time. In the first case, control algorithms are programmatically simulated on a digital computer, and an analog mathematical model of the control object is programmed in the automatic computer, and the ACVK is used as a complex for debugging and verifying control algorithms, taking into account the nonlinearity and dynamics of the control object, which are very difficult to take into account when developing algorithms, if do not constantly solve the differential equations of the object to determine its response to each new control action.
In the second case, for example, when solving differential equations, the general cumbersome problem of approximate calculations is divided into two parts, usually placing computationally intensive calculations in the analog part for which an error of 0.1...1% is permissible.
According to the principle of the above-mentioned division of the task into two parts and the method of organizing the interaction between the AVM and the digital computer, modern digital computers are divided into 4 classes of analog-digital computing
Classes 1,2,3 can be implemented on the basis of the considered structural organization of the ADCC with a simplified UPS built on single-channel ADCs and DACs.
Class 1 is the simplest in terms of organizing the interaction between the AVM and the digital computer. The digital and analog parts operate at different times, and therefore there are no high demands on the synchronization of the operation of the AVM and the digital computer and the speed of the digital computer and the UPS.
Class 2 requires a special organization of alternating operating modes of AVM, DVM and UPS in each cycle of calculations and interaction
Calculation | |||||
Data transfer | Data transfer | ||||
Interrupt | Calculation | Interrupt | Calculation |
Since the AC and CC do not operate simultaneously, there are no problems with their synchronization and no high demands are placed on the speed of the UPS and digital computer. Classes of problems to be solved: optimization of analog model parameters, parametric identification, modeling of random processes using the Monte Carlo method, analog-digital modeling of automatic control systems not in real time, integral equations.
Class 3 requires a different organization of alternating operating modes of AVM, TsVM and UPS.
Calculation | |||||
Data transfer | Data transfer | ||||
Calculation | Interrupt | Calculation | Interrupt |
In phase A, 2 partial tasks of one complex task, compatible in time, are simultaneously performed in the AC and CC. In the CC in phase B, discrete values of function arguments are most often received from the AC and stored, then in phase A, the ordinates of complex functions are calculated from them and prepared for the AC, which in the next phase B are transferred to the AC, where they are stored in analog memories ( SVH), and then are used in the next phase A in analog calculations, etc. Classes of problems to be solved: iterative calculations, solution of ordinary difurs with given boundary conditions, dynamic problems with pure delay of arguments, integral equations, partial differential equations. In class 3, there are no high demands on the speed of the digital computer and digital computer, but precise synchronization of the operation of digital computer and digital computer in phase B is required, since due to the stop of the digital processor, asynchronous control of data transfer is impossible, and synchronous transmission of data blocks is carried out under the control of the direct access controller into memory (KPDP) through the digital computer input/output channel.
Class 4 is most often analog-digital modeling of digital automatic control systems in real time for checking and debugging control digital computer programs in dynamics. It is the most complex in terms of organizing the interaction and synchronization of the operation of the AVM and the digital computer, since here phases A and B are combined, there is a constant mutual exchange of data during the calculation process, and therefore the use of a digital computer and UPS of maximum speed is required.
The structural organization of the UPS, given above and suitable for classes 1,2,3, is not applicable in class 4. The latter class requires a multi-channel organization of ADC and DAC without multiplexing with the additional inclusion of parallel buffer registers at the input and output of the BSC file, exchanging with the OP of the digital computer in direct access mode. The contents of each register are either converted by separate parallel-connected DACs when transmitting data to the AVM, or generated by separate parallel-connected ADCs when transferring data from the AVM to the digital computer.
2.3.3 Features of the ACVK software.
To automate AVM programming using a digital computer and fully automate the analog-digital computing process, traditional general-purpose digital computer software (see Fig. 13.2 p. 398 in the textbook) is supplemented with the following software modules:
1. The processing programs include additional translators from special languages of analog-digital modeling, for example Fortran-IV, supplemented by subroutines in extended Assembly language containing special analog-digital commands, for example, for controlling the analog part using a digital computer program, organizing data transfer between digital frequencies and AC, processing interrupts of central frequency programs initialized by the analog part; an analog-digital compiling system is created;
2. The working, debugging and maintenance programs include an inter-machine exchange driver for controlling the analog part as a peripheral processor, graphic display programs, recording and analyzing results;
3. The library of applied programs includes programs for calculating functions and standard mathematical analog-digital programs;
4. UPS tests and tests of AVM operating units are included in the diagnostic maintenance programs;
5. A whole range of additional control modules is introduced into the OS control programs:
Automation system for analog programming (SAAP), consisting of lexical analyzer; parser(checking the compliance of the analog program entered in the algorithmic language with the rules of recording syntax); block diagram generators(composition and coding of circuits of analog models using the method of reducing order and implicit functions, as in paragraph 2.1); block of calculation programs(scaling the analog model as in clause 2.1, digital software modeling of the analog part on a digital computer with a single calculation to calculate the expected maximum values of variables and clarify the scaling of the analog model, as well as creating a file for static and dynamic control of the analog part after its programming); output presentation programs(display and plotter of the synthesized structure of the analog model, control printout of analog program codes, scale factors, static and dynamic control files);
· Service for synchronization and interaction of automated computers and digital computers (implementation of alternating operating modes);
· Service for processing interrupts initialized by the analog part;
· Program for managing data exchange between AVM and digital computer;
· Program for managing the loading of analog model circuit codes into the SAC (in the RN);
· Program for controlling the static and dynamic control mode (debugging the analog program loaded into the AVM).
Based on the results of automation of analog-digital programming on the magnetic disk of the host digital computer, in addition to traditional digital files, the following additional data files are created, used by the above-mentioned additional modules of the ACVK software: analog block file, switching file (for SAC), static control file, dynamic control file , preparation file for analog functional converters, library of plug-in standard analog-to-digital programs.
2.3.4. Languages of analog-digital modeling.
The considered architecture of the digital computer allows you to describe and enter analog-digital programs only into the host digital computer in high-level algorithmic languages. For this purpose, traditional digital programming languages are supplemented with special operators for describing an analog modeling object, organizing data transfer between the AC and the DC, controlling the analog part using a digital computer program, processing interruptions from the analog part, setting the parameters of the analog model, monitoring the analog part, setting service information, etc. . P.
Universal languages are used, translated by compilation (Fortran IV) or interpretation (BASIC, Gibas, Focal, HOI), supplemented by special subroutines in Assembly, usually called by the Call... operator indicating the identifier of the desired subroutine.
In order to increase the speed of operation of the CAAP, it is usually described and uses specialized analog-digital modeling languages at the input: CSSL, HLS, SL – 1, APSE, and for internal interpretation the Poliz language (reverse Polish notation).
The following analog-digital macro instructions can be entered into universal compiled languages:
1. SPOT AA x– set the potentiometer (DCC) in the analog part with address AA to the position (resistance value) corresponding to the digital code value stored in the digital computer OP at address x;
2. MLWJ AA x– read the analog value at the output of the operating unit in the AC with address AA, subject it to analog-to-digital conversion, and write the resulting digital code into the digital computer OP at address x. The interaction between the analog part and the digital part can be described as a procedure call:
Call JSDA AA x, where JSDA is the corresponding identifier of a plug-in subroutine in Assembly language, for example, an installation procedure - set the value x from the DAC output to address AA in the analog part.
Therefore, it is very important to understand how the type of parallelism of the problem being solved affects the way the parallel computer is organized.
3.1.1 Natural parallelism
independent tasks.
It is observed if there is a flow of unrelated tasks in the aircraft. In this case, increasing productivity is relatively easily achieved by introducing into the “coarse-grained” BC ensemble independently functioning processors connected to the interfaces of the multi-module OP and initialization of input/output processors (I/O).
The number of OP modules is m>n+p in order to ensure the possibility of parallel access to memory of all processing processors and all PVVs and to increase the fault tolerance of the computer. Backup (m-n-p) OP modules are necessary for quick recovery in the event of a working module failure and for storing in them the SSP of processors and processes at program checkpoints required for restart in the event of a processor or OP module failure.
An opportunity is created for each of the tasks to be solved to temporarily combine the pair: Pi+OPj as an autonomously functioning computer. Previously, the same OP module worked in pairs: PVVk + OPj, and in OPj the program and data were entered into the input buffer. At the end of processing, an output buffer is organized and filled in OPj, and then the OPj module is inserted into the OPj+PVVr pair for exchange with the peripheral device.
The main task of organizing computing processes, solved by the “dispatcher” system program, is the optimal distribution of tasks between parallel processors according to the criterion of maximizing their load, or minimizing their downtime. In this sense, it is optimal asynchronous the principle of loading tasks into processors without waiting for tasks to be processed in other busy processors.
If a package of input tasks accumulated over a certain time interval is stored in the VRAM, the problem of optimal asynchronous scheduling comes down to creating an optimal schedule for when tasks are launched on different processors. The main input data required for this is a set of known expected computational processing times for all tasks of the accumulated batch, which are usually indicated in the control cards of their tasks.
Despite the independent nature of the tasks in the totality of their asynchronous computing processes, conflicts between them for shared computer resources are possible:
1) Services of a common multi-system OS, for example, processing I/O interrupts, or calls to a common reliability OS during failures and restarts;
(О–) – ®О-Д – change of sign of D.
With an operation in layer I, two operations each in layers II and III could be performed in parallel if the ALU had a corresponding excess of operating blocks.
The parallelism of operations discussed above in solving differential equations and when processing matrices belongs to the regular class, since the same operation is repeated many times over different data. The last example of a quadratic equation has irregular parallelism of operations, when different types of operations can be performed simultaneously on different data.
As shown above, for using regular parallelism of operations while improving performance, it is suitable matrix organization Aircraft with general control.
In the general case of irregular parallelism of operations, a more suitable way to improve performance is considered streaming organization Computers and aircraft. In streaming computers, instead of the traditional von Neumann program control of the computing process in accordance with the order of commands determined by the algorithm, the reverse principle of program control is used according to the degree of readiness of the operands, or the data flow (operand flow), determined not by the algorithm, but by the operand graph (data transfer graph ).
If there is a sufficient excess of processing devices in a parallel processor, or an ensemble of redundant microprocessors in a computer system, then naturally and automatically (without special scheduling and launch scheduling) those parallel operations whose operands were prepared by previous calculations will be simultaneously executed.
The computational process begins with those operations whose operands are the original data, for example, in the first layer of the GPA of a quadratic equation, three operations are simultaneously performed, and then it develops as the operands are ready. After this, the multiplication command is called, then the subtraction and check of the logical condition, then the macrooperator (Ö) and only after that - two commands at the same time: addition and subtraction, and after them - two identical division commands.
The technical implementation of the flow organization of aircraft is possible in three ways:
1) The creation of special streaming microprocessors, which belong to the class of specialized ones and will be discussed in the next semester;
2) Special organization of the computing process and modification of low-level machine language in multi-microprocessor ensemble computers built on standard von Neumann microprocessors;
3) The creation of processors with an excess of the same type of operating units and the addition of operating systems using a stream method for organizing the computing process (implemented in the domestic stream processor EC2703 and the Elbrus-2 supercomputer).
sampling systems
and message quantization
Omsk 2010
Federal Agency for Education
State educational institution
higher professional education
"Omsk State Technical University"
Digital modeling of sampling systems
and message quantization
Guidelines for laboratory tests
works for distance learning
Educational and laboratory complex for digital modeling of a system for quantizing continuous messages by level …………………
General provisions……………………………………………………………..
Description of the package………………………………………………………………………………….
Description of interfaces……………………….………………………...
Description of classes………………………….…………………………….
Connection block diagram…………………………..…………………
General information…………………………………………………………….
Functional purpose of the complex…………………………………….
Installation procedure in the NetBeans development environment…….………………….
Description of the class library……………………….………………………
Purpose of laboratory work.……………………………………………………………...
Purpose of the study……………………………………………………………..
Work order………….…………………………………….....
Construction of a digital model…………………………………………………………….
Test questions for laboratory work…………………
Educational and laboratory complex for digital modeling of a system for quantizing continuous messages by level
1. General Provisions
Modeling- one of the most common ways to study various processes and phenomena. There are physical and mathematical modeling. In physical modeling, the model reproduces the process being studied while preserving its physical nature. The advantage of physical modeling over a natural experiment is that the conditions for implementing a model process can differ significantly from the conditions inherent in the original process, and are selected based on the convenience and simplicity of the study. But physical modeling has a limited scope. Mathematical modeling has obviously broader capabilities.
Modeling is a process consisting of two, generally repeated, stages:
constructing a model similar to the original object that is difficult to access for direct research;
research (design) of the original object using the constructed model.
When studying any process using the method of mathematical modeling, it is necessary first of all to build its mathematical model. A mathematical model is necessary to construct a modeling algorithm. There are several main ways to use a mathematical model algorithm:
analytical study of processes;
study of processes using numerical methods;
hardware modeling (on analog computers and special modeling installations);
modeling of processes on a digital computer.
Currently, the method of statistical modeling implemented on a digital computer has become widespread. This type is an integral part of mathematical modeling.
Digital modeling has a number of advantages over other research methods (versatility, flexibility, cost-effectiveness) and allows us to solve one of the main problems of modern science - the problem of complexity.
Educational and laboratory complexes are designed for the study and research of such information systems that carry out the formation, sampling (quantization), encoding, transmission, storage, decoding and restoration of messages. These systems consist of real blocks that perform the listed transformations. These include:
source (generator, shaper) of the message;
sampler (quantizer, quantization unit);
encoder (encoder, coding unit);
link;
memory block (delay line);
decoder (decoder);
message receiver.
Digital models that simulate the operation of these blocks are presented in educational and laboratory complexes in the form of separate object classes or can be formed from them. These objectclass complexes serve the following purposes:
to simulate an experiment in order to obtain data for the design of these systems;
to automate the calculation of parameters, synthesis of functions of individual blocks and the system as a whole;
for modeling, simulating and displaying work:
systems for sampling continuous messages over time;
message quantization systems by level;
efficient coding systems;
noise-resistant coding systems;
combinations of these systems.
for plotting graphs.
Let's consider some features of studying the operation of systems through their digital modeling. It is usually aimed at studying the effectiveness of systems. In this case, the interaction of this system with another system, called the external environment, is modeled. The efficiency of any system is determined by two groups of factors: the properties and characteristics of the external environment; functions and parameters of the simulated system. The most effective operation (behavior) of the system is in a situation where the properties and characteristics of the external environment are “coordinated” with the functions and parameters of the system. Indicators and criteria for the effectiveness of the system are set (defined) by its developers, since they cannot be established by formal methods.
The study of work efficiency under “normal conditions” is carried out by organizing the most probable normal (standard) situations determined by the external environment, which are presumably known to the developer or researcher. In this case, specific situations are specified by the most typical properties and characteristics of the external environment.
In addition, studies are carried out of the behavior of the system in extreme conditions and unlikely situations, which are determined by sets of properties and characteristics of the external environment that are poorly predictable for the researcher (maximum values of its characteristics, such as, for example, the prohibitive value of current in an electrical circuit, overloads, large-amplitude interference and frequencies, physical destruction of the system or its components due to defective materials, etc.).
The situation set by the external environment (standard or abnormal) is modeled by fixing some of its properties and characteristics. At the same time, the efficiency of the systems is studied by varying its functions and parameters. It is also possible to study the system in a different order, in which the functions and parameters of the system are recorded and the properties and parameters of the external environment are varied. Assuming that the properties of the external environment and the functions of the system under study, among other things, are represented by sets of measured and controlled (variable) numerical characteristics and parameters.
At the next iteration of studying the behavior of a system, the entire set of characteristics of the environment and system parameters are usually fixed. In this case, one of the listed components is varied within the “plausible” acceptable range. The performance indicators of the system are determined for many values of the variable parameter and entered into the research protocol, usually drawn up in the form of a table. At the next iteration of the study, another parameter is varied, and the rest are fixed.
Usually, a complete search of parameters and their values (even with computer modeling) cannot be carried out due to time constraints. Therefore, a developer or researcher often has to carry out a certain ordered and directed selection of parameters and characteristics. In combination with the possibility of computer automatic selection of parameters, this allows you to reduce the time of system research. In addition, developed methods for designing experiments should be used.
When digitally modeling a system for quantizing continuous messages by level in laboratory classes, the properties of the external environment are represented by a certain form of the transmitted signal, which does not change during the research process, as well as by a normally distributed (Gaussian) random noise acting in the communication channel. The numerical characteristics of the interference are represented by the mathematical expectation and the standard deviation of its amplitude.
The function of the system in this lab is to quantize continuous messages by level (parameter amplitude). The quantizer parameters are represented by the range of continuous message values and the number of quantization levels (or quantization step).
The concept of logic modeling Logical modeling is understood as a complete and accurate software reproduction of the behavior of a digital circuit according to its functional and/or structural description and given sets of input signals. In manual design, the model is represented by a working layout or prototype (prototype). In computer-aided design, the current layout is replaced by a simulation (software) model of the project, and full-scale or physical experiments are replaced by model (machine) ones. It is easy to make any changes to the model and thus improve the project until it reaches the required quality.
Problems solved by the method of logical modeling 1. The main task of logical modeling is to check the correct functioning of a digital circuit before its actual (physical) implementation 2. Study of the timing characteristics of the circuit - speed, execution time of operations, maximum counting or shift frequencies. Detect race conditions and crash risks. Delays. 3.Control of timing relationships - preset time and hold time, minimum signal duration. 4.Development of control and diagnostic tests. Fault modeling. 5. Comparison of alternative circuit solutions and selection of the most suitable one. "The Tyranny of Alternatives." Up to 70% of the time working on a project is spent on its verification
Problems solved by the logical modeling method 6. Monitoring the output of components to the permissible load. 7. Monitoring of circuit components for permissible power dissipation. 8. Identification of uninstallable elements using reset or initialization signals. 9. Performing statistical assessments, for example, determining the percentage of yield of suitable circuits, which cannot be done on single prototypes. 10. Conducting climatic, most often temperature, tests.
Logic Modeling Process Simulation is performed in a similar manner to manual circuit verification. While experimenting with a working layout, the engineer sets the voltage levels at the circuit inputs and observes the output signals on the oscilloscope screen. In the case of logic modeling, he simulates these actions using a special program called a modeler (simulator, imitator). The difference is that real, physical signals are replaced by software generated ones and they are observed not on an oscilloscope, but on a monitor screen.
The process of logical modeling From the point of view of data processing, modeling comes down to three main processes: Drawing up a description of the simulated circuit in a certain language (LOO - object description language) and entering it into a computer. The description can be specified in the form of a diagram, a list of components and connections (NetList), in the form of a tabular presentation, or in the form of a state diagram of the target audience. Controlling the description (for example, searching for floating inputs, shorted outputs, duplicate names) and translating it into object code. ERC control program - Electrical Rules Check. Performing experiments with a software model that simulates the operation of the circuit. Before starting the simulation, sets of input signals, the initial state of the circuit, control points for observation, and the final simulation time are specified.
Graphical representation of the logic modeling process Input of a circuit description NetList Libraries of graphical descriptions of components Automatic generation of a circuit model Libraries of mathematical models of nuclear weapons components Designer & Y=A and B; Circuit modelModeler proceduremain Simulation tools Input signal diagrams Initial state of the circuit Output control Special conditions Simulation method Simulation results Operating program NPO M1 – delta principle T M2 – delta principle Z min typical max fault temperature Compiling simulation Linker Linker
Models of digital signals The range of problems solved by the logical modeling method is determined primarily by the number of distinguishable states that a digital signal can take. Each state is associated with its own individual symbol, and their combination constitutes the modeling alphabet. The simplest alphabet - binary, used in old AFM, contained a bit set (0, 1). Since in this case any signal can take only two values (0 and 1), the change in the logical level had to be considered instantaneous. Real signal Threshold Binary approximation Event - instantaneous switching Advantage - economical. Allows you to solve only one main modeling task - checking the operation of the circuit
Models of digital signals With ternary modeling (0, 1, X), the switching signal can be depicted more realistically, for example 0X1 or 1X0. Such a recording means that when the state of an element changed, its output signal for some time (while a rise or fall was forming) had an indefinite value. 0 1 X Switching 0X1 Switching 1X0 0 1 X 0X1 Active-HDL 8.1 X – unknown value The three-digit alphabet (0,1,X) is used in the PML language (CAD PCAD 4.5) X is assigned to the signal at the output of the LE during the transient process. X is assigned to the trigger outputs after prohibited combinations of signals are applied to its inputs X is assigned to the trigger outputs at the beginning of the simulation, when its state is unknown
Models of digital signals When modeling components with dynamic inputs (flip-flops, counters, registers, memory), it is very convenient to record the moments when signals switch in one direction or another. For this purpose, two more values are added to the modeling alphabet: or/or R (from the word Rise - front) - switching the signal up; or \ or F (from the word Fall - decline) - switches the signal down. CAD OrCAD 9.1 (PSpice projects) uses a six-digit alphabet (0,1,X,R,F,Z)
Models of digital signals To model bus structures, another Z-state is introduced into the alphabet of permissible signal values, that is, a state of high impedance at the output when it is actually isolated from the load: (0,1,X,R,F,Z). The four-digit alphabet (0,1,X,Z) is very common. It is used in such hardware description languages as Verilog, ABEL, AHDL (Altera), DSL (DesignLab). The four-character alphabet is often called the FPGA synthesis alphabet.
Models of digital signals For a more accurate representation of signals (more adequate modeling), you can use two main techniques: Expand the modeling alphabet (we have already done this); Introduce the concept of logical signal strength (strength level). As an example, consider the extended modeling alphabet of the VHDL language type bit is (0,1); - basic, built-in signal type. Alphabet (0,1) type std_ulogic is (U,X,0,1,Z,W,L,H,-); - extended signal type. Alphabet (U,X,0,1,Z,W,L,H,-) The extended signal type is located in a separate package std_logic_1164, located in the ieee library. Therefore, to include this type of signals in the model, you need to place the lines in front of it:
Models of digital signals Language VHDL Alphabet (U,X,0,1,Z,W,L,H,-) U – from the word Uninitialized – literally “not initialized” This means that the signal in the program was not assigned any values at all ; provides control of the correctness of initialization - - indifferent state (Dont Care) This means that the signal can take any of the allowed values, which will not affect the operation of the circuit. In books and reference books, the indifferent state is often denoted by the symbols “d” or “*”. JK flip-flop R C J K Q NQ Reset 1 * * * 0 1 When synthesizing a CA in forbidden states, instead of “*” you can put 0 or 1 and get different circuit solutions. In CAD, the choice of a specific value is left to the compiler in order to optimize the designed device. Example. DSL language in CAD DesignLab 8. In the expression Y =.X.; the PLSyn compiler will set Y = 0 by default;
Digital signal models Active-HDL 8.1 Graphical representation of digital signal values. The concepts of strong (force) and weak (weak) signals X – forcing unknown 0 – forcing zero 1 – forcing one W – weak unknown L - weak zero (weak zero) H - weak one (weak one) A weak signal is formed from sources called drivers. They have high output impedance compared to strong signal sources. For example, an open collector or emitter circuit.
Models of digital signals SDRZ 0S0D0R0Z0 1S1D1R1Z1 XSXDXRXZX Let's return to the concept of logical signal strength (strength level). We already know that expanding the capabilities of modeling and increasing its adequacy can be achieved not only by increasing the modeling alphabet, but also by introducing the concept of “level of logical signal strength”. This idea was first implemented in the PML language of the PCAD 4.5 package. Example: The Verilog language has only a 4-digit modeling alphabet (0,1,X,Z), but at the same time 8 logical strength values. Logical strength S > D > R > Z D>R>Z"> 
Models of logical elements When constructing models of logical elements, the following properties can be taken into account: the function being performed; signal propagation delay; load capacity; response thresholds; duration of fronts; random spread of delays; temperature changes in parameters (for example, time delays, levels of logical zero and one, etc.). Note that the higher the importance of the modeling alphabet and the more properties are taken into account in the model, the more resources (processor time and memory) are required to run the model. For this reason, in modern modeling systems, the number of allowed values of a digital signal usually does not exceed 4..9, and of the possible properties, as a rule, only function, time delay and load capacity are modeled.
Boolean Models Boolean gate models work with the binary alphabet (0,1) and can be implemented as: a logic equation, a truth table, or an algorithm block diagram IN1 IN2 OUT1 & AND2 IN1 IN2 OUT1 & AND2 IN1 IN2 OUT1 & AND2 F1 F2 Y1 Flow circuit description: Y1 = A & B; (PCAD 4.5, PML language) Y1 = A * B; (DesignLab 8, DSL language) Y1
PROCEDURE AND2 (INPUT IN1, IN2 ; OUTPUT OUT1); TRUTH_TABLE IN2, IN1::OUT1; 1, 1:: 1; END TRUTH_TABLE; ENDAND2; Boolean models IN1 IN2 OUT1 & AND2 IN1 IN2 OUT1 & AND2 IN1 IN2 OUT1 & AND2 F1 F2 Y1 IN1IN2OUT Algorithmic description Tabular description Language DSL Start End IN1=0 IN2=0 OUT1=0OUT1=1 Yes No Yes No
Boolean models Typically, Boolean models are used for synchronous clock-by-cycle modeling (delta T principle) without taking into account delays. This is the most primitive modeling. Its main advantage is simplicity and efficiency. In Boolean modeling, time is divided into clock cycles (t principle). The duration of the cycle is selected so that within one cycle no signal switches more than once. The actual switching is transferred to the beginning of the cycle within which it occurred. Switching is considered instantaneous. The signal propagation delay from input F1 (or F2) to output Y1 is not modeled, since both switchings are transferred to the beginning of clock T2 (or T4) and become simultaneous. Model time F1 F2 Y1 Clock Real signal Boolean model T0T1 T2 T3T4T5T6 Risk of failure Instant “Needle” event Glitch
Boolean Models Typically, one clock cycle corresponds to one set of input signals and is processed in one cycle of the modeler. With each cycle, a unit is added to the model time counter, that is, the model time advances by clock cycles in accordance with the expression: T:=T+1. In a real circuit, due to the overlap of the fronts of the signals F1 and F2, a short pulse may appear at the output of element 2I - a risk of failure (cycle T6). Boolean models are not able to predict the appearance of such needles, which are very dangerous for the operation of digital equipment. Boolean modeling solves only one main task of any modeling - checking the correct functioning of digital equipment
Ternary models Ternary models, unlike Boolean models, simulate the occurrence of transient processes when signal levels change. In ternary modeling, a beat is divided into two half-beats. During the first half-cycle, the switching signal takes on the value X (changes), and on the second half-cycle it reaches a new value. Ternary models use a three-digit alphabet (0,1,X)
Ternary models Model time F1 F2 Y1 Real signal Failure risk 0 1 X Failure risk model Ternary model 1 X X Tick T6 Half-cycle of uncertainty Half-cycle of certainty IN1 IN2 OUT1 & AND2 IN1 IN2 OUT1 & AND2 IN1 IN2 OUT1 & AND2 F1 F2 Y1 IN1IN2OUT IN1IN2OUT1 0X0 X00 1XX X1X XXX M2 M3 1X0 0X1 0X0 truth table of element 2I for three-valued logic
Ternary models The risk of failure is indicated by identical signal values at adjacent clock cycles and the X value at the half-cycle of uncertainty between them. 0011XX Risk of failure Ternary modeling reflects only the fact of signal switching and does not specify how long the switching lasted and where exactly within the clock cycle it occurred. In other words, the duration of the X-state in ternary modeling is always equal to half a cycle and is in no way related to the real signal switching time.
Multivalued models Multivalued models make it possible to more accurately describe the behavior of real elements, however, compared to ternary models, they do not contain anything fundamentally new. For comparison, consider the truth tables of element 2I for binary, ternary and five-digit modeling. OUT1 IN2 01X IN X X0XXXX 0 X X 0 XX IN1 IN2 OUT1 & AND2 IN1 IN2 OUT1 & AND2 IN1 IN2 OUT1 & AND2 F1 F2 Y1 X ? IN1 IN2 OUT1 & AND2 ? IN1 IN2 OUT1 & AND2 M2M3 M5
Models of logical elements taking into account delays These models, unlike ternary ones, simulate delays explicitly. To display the delay, you must indicate the true position of the switching signal on the time axis. Modeling delays with a clockwise method of advancing model time (delta T principle). To reflect the delay, it is necessary to increase the time resolution, that is, divide the clock into smaller units of time, called quanta (microcycles) or steps. For example, in the PCAD package, a cycle is called CYCLE, and a quantum is called STEP. 1 A Y A Y Quantum Cycle tз = 8 quanta Delay is represented as an integer - the number of quanta
Models of logical elements taking into account delays In models taking into account tз, the cycle is explicitly cut into quanta. Moreover, the quantum value should be a small part of the delay, for example 1ns. The operating cycle of the simulating program is now tied not to a clock cycle, but to a quantum. Therefore, in order to simulate the operation of the circuit during one clock cycle, the modeler will have to perform a much larger amount of work, namely, as many cycles as there are quanta placed on the clock cycle length. Now, with quantum accuracy, you can indicate the moments of true switching at the inputs and outputs, and also calculate the propagation delay using an integer number of quanta. All that remains is to model it. The classic model of a logic element taking into account delay contains two blocks. The first one implements logic (function), the second one implements pure delay. φ tз = 0 B A C YсYс Y Logic block Delay block Yс (from the word synchronous) instantly responds to changes in input signals Dynamic model in PSpice projects
Models of logical elements taking into account delays AYсYс Logic block LOGICEXP PINDLY Counter tз Container Yc Container Y Y NextCurrent Stores the future value Stores the current value Delay block Possible implementation of a delay block for clock-by-cycle modeling The delay counter works for subtraction. When the Yc output is synchronously switched, the new value is written to the container of future values, and the delay with which the new Yc value should appear at the Y output is entered into the counter tз.
Models of logical elements taking into account delays In the process of advancing the model time (tquanta = tquanta + 1), the delay in the counter tз decreases, but does not “melt” to zero. The future output value becomes the current value, which means that the contents of the left container must be rewritten into the right one. Modeling delays with an event-based mechanism for advancing model time (delta Z principle). We considered the option when the delay is modeled inside each logical element. This solution leads to significant expenditure of instrumental computer resources. Another possibility to model a real delay is to plan a new event at the output and calculate the moment of its occurrence t(Y) according to a simple rule: t(Y) = t(Yс) + tз But t(Yс) is the current model time t (current) This means that for any event (switching) you can plan the time of occurrence of a future event as t(future) = t(current) + t(delays)
Models of logical elements taking into account delays The calculated event is placed by the modeler in the queue of future OBS events, which is sorted in chronological order. As you can see, all the work of simulating delays is transferred to the modeler, which only needs to indicate the delay value relative to the current model time. Note that it is no longer necessary to round it to a whole number of quanta. In VHDL this is done very elegantly: Y
Digital modeling at the present stage is developing most dynamically. This is due to the intensive development of mathematical software, formed in the form of application software packages. The use of these packages improves the productivity of modeling and at the same time simplifies it.
Advantages of the digital modeling method:
1. Any class of problems subject to mathematical interpretation is solved;
2. High accuracy of the solution (limited only by the time it takes to solve the problem);
3. Ease of transition from one task to another (you just need to restart the program);
4. Possibility of studying high-dimensional objects.
Disadvantage of the digital modeling method– final simulation time, which may not coincide with real time.
A digital computer is a complex of technical devices in which processes can occur that display (model) actions with numbers. It is actions on numbers that constitute the essence of computational operations in the numerical solution of various mathematical problems. Modeling the process of numerically solving a mathematical problem on a digital computer practically means automatically solving it using a digital computer.
Numbers can not only express the meaning of constant and variable quantities, but also be symbolic conditional models of a wide variety of other objects - letters, words, objects, phenomena, etc. This makes it possible to reduce various non-computational tasks to operations on numbers, for example, determining the number of objects with given properties. Thanks to this, it is possible to simulate on a digital computer the procedure for solving a non-computational problem, i.e. machine implementation of this solution.
The process of functioning of any material object represents a sequential change of its states in time, each of which is determined by specific values of certain physical quantities. If the object is a continuous system, then these quantities are continuous functions of continuous time.
A mathematical description of an object consists of various mathematical forms of expressing quantitative relationships between variables and constants. These are various functions, equations, systems of equations, conditions for the uniqueness of their solutions, inequalities and other mathematical representations.
If a mathematical description of the functioning of the original object is known, according to this description a process is defined on numbers expressing the values of quantities characterizing the state of the object, and this process is displayed in a digital computer, then the process implemented by the digital computer is a material functional formal mathematical similar digital model of the original.
The discrete nature of the functioning of a digital computer requires, as a rule, the reduction of the original mathematical description of the original to a form convenient for digital modeling. First of all, discretization of continuous quantities is necessary. In this case, continuous functions are subject to quantization by level and argument. As a result, a continuous function of a continuous argument y = f(t) turns into a discrete function of a discrete argument
T y k y = f (Tk),
where k and k y are numbers taking values 0, ± 1, ± 2, ± 3, ... ; T and Ty are quanta of the variables t and y.
Level quantization is the replacement of the y value with a corresponding number of a certain bit depth, accompanied by a rounding error
Dy< T y /2.
Since in modern digital computers the number of digits is large (32 or more) and the error is negligible, therefore, in practice we can assume that the functioning of digital computers is described by lattice functions of the form
y = f (Tk) = f [k]
and models them.
Digital modeling of the original requires algorithmization of the mathematical description of the original. An algorithm is a precisely defined rule for performing calculation operations on numbers, the sequence of which constitutes the general process of converting source data into the result of solving the corresponding problem. Algorithmization of a mathematical description consists of obtaining an algorithm corresponding to this description. If, for example, the functioning of the original is described by a differential equation, then algorithmization consists of compiling an algorithm for the numerical solution of this equation. Essentially, the algorithmization of a mathematical description consists of bringing it to a form convenient for digital modeling. It is performed on the basis of the selected numerical method for solving the problem, which allows you to reduce the solution to arithmetic operations. In this case, it is often useful to use the apparatus of lattice functions.
An algorithm can be presented in three main forms: analytical, verbal and structural.
The analytical form of an algorithm is its expression as an explicit function of the corresponding arguments or as a recurrent formula. The form is very compact, but its application possibilities are limited.
The verbal form of an algorithm is its description in natural language, detailed instructions for a person solving a problem manually on paper. The form is universal, but is cumbersome and lacks visibility.
The structural form of an algorithm is its description in the form of a block diagram consisting of individual blocks connected by straight lines. Each block corresponds to some operation on numbers. The form is universal, compact and visual. Therefore it is used most often.
In general, the digital computer modeling process consists of the following stages:
1. Drawing up the initial algorithm, i.e. algorithmization of the mathematical description of the original.
2. Drawing up an intermediate algorithm in an algorithmic language.
3. Obtaining a machine algorithm.
4. Debugging the program.
5. Machine implementation of the problem solution.
The first four preparatory stages are significantly simplified through the use of standard algorithms and corresponding standard programs, pre-compiled and repeatedly used to solve problems such as calculating elementary functions, determining the zeros of polynomials, converting numbers from one number system to another, etc.
A set of software tools designed to reduce the labor intensity of preparatory work, increase the efficiency of using a machine and facilitate its operation is called digital computer software.
In digital modeling, one most often has to deal with lattice functions f[k], corresponding to continuous functions of a continuous argument. The continuous function that coincides with the discretes of a lattice function is called the envelope of that lattice function. Each continuous function f(t) can serve as the envelope of various lattice functions f i [k] = f(T i k), differing in the parameter T i - the sampling period of the function f(t). Each trellis function can have many different envelopes.
Various mathematical forms and representations that characterize or define the continuous function f(t) can be associated with analogues that characterize or define the lattice function f(k). An analogue of the first derivative of the function f(t)
are the first difference equation of the function f[k]
Those. a transition is made to numerical methods of solution.
So, finally,
* The first stage in design is the selection of the most suitable mathematical model. This stage should ensure the receipt of the most successful mathematical model and the development of requirements for the conditions of the model;
* The second stage of the design process is the preparation of a mathematical model for simulation. The problem is solved by bringing the discrete process to a block diagram and bringing the system of equations to a discrete form. This stage ends with two results: a mathematical description and a block diagram of the entire discrete system. The structural diagram of the resulting discrete system must be identical to the structural diagram of a continuous system in terms of information flow;
* the third stage is writing a program to carry out mathematical modeling. This is a decisive stage, containing strict adherence to time relationships in the synthesized mathematical model; as a rule, the greatest number of problems arise during the transition from problems of the 2nd stage to problems of the 3rd stage;
* the fourth stage is testing, checking and debugging the model, after which a completed model is obtained.